The present invention generally relates to a method for forming a DRAM capacitor that has improved charge storage capacity and device made by such method and more particularly, relates to a method for forming a DRAM capacitor that has improved charge storage capacity by forming a zig-zag sidewall in the capacitor cell and device made by such method.
In the design of VLSI and ULSI memory devices, a structure of DRAM is frequently used for its simplicity in fabrication and its high unit capacitance when designed in a stacked structure. The DRAM memory cells have been named dynamic because they can retain information only for a limited time and then they must be read and refreshed periodically. The operation of a DRAM cell is therefore in contrast to a static random access memory cell which does not require periodic refresh signals in order to retain stored data. In a typical DRAM cell, the structure includes a transistor and a storage capacitor. When DRAM cells were first developed, planar type storage capacitors which occupy large wafer surface areas have been used. As the circuit density increases in modern semiconductor devices where smaller chips are being made and being packed with ever-increasing number of circuits, i.e., devices fabricated by the ULSI technology, the specific capacitance of a storage capacitor must be increased in order to meet such demands.
Researchers in the technology of semiconductor processing have tried different approaches in efforts to achieve higher capacitance on limited usage of chip real estate. For instance, one of such approach is to store charges vertically in a capacitor which is built on top of transistor and thus allowing a smaller cell to be built without losing storage capacity. Other researchers have proposed the use of a fin-type capacitor structure to further improve the storage capacity of the DRAM capacitor. A DRAM capacitor is typically formed by at least two layers of semi-conducting materials and one layer of a dielectric material. For instance, a typical DRAM capacitor utilizes a thin oxide layer sandwiched between two polysilicon layers for producing a high capacitance capacitor cell. In the stacked structure, the capacitor can be built by stacking over the bit line on the surface of a silicon substrate. The effective capacitance of a stacked cell is increased over that of a conventional planar cell due to its increased surface area.
The stacked capacitors which include the fin-type stacked capacitors have been successfully used in 16 MB DRAM devices. However, as device density increases to 256 MB or higher, the planar surface required for building a conventional stacked capacitor becomes excessive and thus cannot be tolerated. Other techniques are thus needed to further improve the unit capacitance of a DRAM stacked capacitor cell.
It is therefore an object of the present invention to provide a method for fabricating a DRAM capacitor in a stacked structure that does not have the drawbacks or shortcomings of the conventional DRAM stacked capacitors.
It is another object of the present invention to provide a method for fabricating a DRAM capacitor that has improved storage capability without increasing the chip real estate usage.
It is a further object of the present invention to provide a method for fabricating a DRAM capacitor that has improved charge storage capacity by increasing the surface area available in the contact hole for forming the capacitor.
It is another further object of the present invention to provide a method for fabricating a DRAM capacitor that has improved charge storage capacity by forming a zig-zag sidewall structure in a contact hole for forming the capacitor.
It is still another object of the present invention to provide a method for fabricating a DRAM capacitor that has improved charge storage capacity by forming a contact hole in multiple layers of insulating materials of BPTEOS oxide and PETEOS oxide such that a zig-zag contact hole can be formed.
It is yet another object of the present invention to provide a method for forming a DRAM capacitor that has improved charge storage capacity by wet etching a contact hole formed in alternating layers of BPTEOS oxide and PETEOS oxide materials with an etchant that has sufficiently high etch selectivity toward PETEOS oxide in order to form a corrugated sidewall in the contact hole.
It is still another further object of the present invention to provide a method for fabricating a DRAM capacitor that has improved charge storage capacity by adding a layer of undoped silicate glass between a BPTEOS oxide layer and a PETEOS oxide layer such that shorting between a Poly 2 layer and a Poly 3 layer is eliminated.
It is yet another further object of the present invention to provide a method for fabricating a DRAM capacitor that has improved charge storage capacity by first performing an anisotropic etching process for forming a straight contact hole and then a wet etching process for forming a zig-zag sidewall in the contact hole.
In accordance with the present invention, a method for forming a DRAM capacitor that has improved charge storage capacity is provided in which a zig-zag sidewall of a capacitor cell is formed such that the surface area of the capacitor cell is increased and thereby increasing its charge storage capacity.
In a preferred embodiment, a method for forming a DRAM capacitor that has improved charge storage capacity can be carried out by the operating steps of first providing a preprocessed semiconductor structure which has a gate structure formed on top, then alternatingly depositing first a BPTEOS oxide layer and then a PETEOS oxide layer on top of the structure such that at least one BPTEOS oxide layer and at least one PETEOS oxide layer are formed on top of the structure, then anisotropically etching a contact hole substantially vertical sidewalls exposing the edges of the PETEOS oxide and the BPTEOS oxide layers, then wet etching the semiconductor structure with an etchant which has a sufficiently high etch selectivity toward the PETEOS oxide layers such that a substantially uneven sidewall is formed in the contact hole, and then depositing and forming subsequent conductive and dielectric layers forming the DRAM capacitor.
In another preferred embodiment, a method for improving the charge storage capacity of a DRAM capacitor can be carried out by the steps of first providing a pre-processed semiconductor structure that has a gate structure formed on top, then depositing a first layer of BPTEOS oxide on top of the gate structure, then depositing a first layer of PETEOS oxide on top of the first BPTEOS oxide layer, then depositing a second layer of BPTEOS oxide on top of the first layer of PETEOS oxide, then depositing a second layer of PETEOS oxide on the second layer of BPTEOS oxide, then anisotropically etching a contact hole of substantially vertical sidewalls to expose the edges. of PETEOS oxide and BPTEOS oxide layers, then wet etching the semiconductor structure with an etchant that has a sufficiently high etch selectivity toward the PETEOS layers such that a zig-zag sidewall is formed in the contact hole, and depositing and forming subsequent polysilicon and dielectric layers to form the DRAM capacitor.
In still another preferred embodiment, a method for forming a DRAM capacitor that has increased charge storage capacity can be carried out by the operating steps of first providing a pre-processed semiconductor wafer, then depositing a first BPTEOS oxide layer on the wafer, then depositing a buffer layer on the first BPTEOS oxide layer, the buffer layer protects a previously formed electrode from being shorted by a subsequently deposited electrode layer when the BPTEOS oxide layer is subjected to a wet etch process, then depositing a first PETEOS oxide layer on the buffer layer, then repeating the deposition process for the BPTEOS oxide layer and the PETEOS oxide layer until at least two BPTEOS oxide layers and at least two PETEOS oxide layers are deposited on top of the wafer, then anisotropically etching a contact hole of substantially vertical sidewalls to expose the edges of the PETEOS oxide layers and the BPTEOS oxide layers, then wet etching the semiconductor wafer with an etchant which has a sufficiently high etch selectivity toward the PETEOS oxide layers such that a substantially uneven sidewall is formed in the contact hole, and then depositing and forming subsequent polysilicon and dielectric layers forming the DRAM capacitor.